SomaKruze's messages

For your question on kohctykop (or however it is spelled):
Your two circuits work differently because of the propagation delay (as mentioned in the video). The electricity flows from one of the longer ends of any circuit to the other. The semiconductor in the middle acts as a conditional, requiring a specific condition to work. In an NPN gate (red on the ends), when power is given to the middle yellow, it enables electricity to flow from the powered end of the red silicon to the other end. In a PNP gate (yellow on the ends) the absence on power flowing through the red makes it possible for electricity to transfer between the two yellow ends. Whenever power is supplied/taken away from the middle of a logic gate, it is said to be “changing its state.” While the electricity travels instantly, changing state requires a small amount of time, which is the propagation delay. You can eliminate propagation delay by supplying/removing power first to the center of a gate, which will then let electricity pass by it without the delay. For example, load this with Level 1: eNrtmssNgzAQRPEOF2pIC7mnlvTfSISTU2IbZPAvPMBcnoZdhBnWWub7fFuebnm4
ecrZEdYQujyh5QqnfOFUPaLbKw4LLe8eHXMVIUKECBH2JfTlnMU3TyUFx3FqWg9F
4pakawry55jWzApQvYOG6UeuBI3eERTaJ03OZ0u/CxFa0JGiTrjLKv+TqtOcdamn
AIWOQS9slVAoFIpVbtWNKldzbmnTC5YApuaEQrHKVktsNYsrFuBQKFY5CFWvOWOV
UOigVjlmjztpO4r40ikd8MSVbYseqUih0P6oZfW407RMj/sUqwyP47TZt8On8PsX
Q4W4gaBf2vpZQaHlVkkF5nMDR3oBXoXG/Q==
Note that because power if being supplied to the center part of the top gate, the power from A0 can pass through freely. In the bottom gate, Power is being supplied to the red end, and A0 is wired to the middle. This creates the delay when A0 turns on, and causes the bottom gate to change states (whereas the top gate has already changed states, so there was no delay.) and slightly delay the power traveling through from +VCC. Run the verification test and note that Y0 matches A0, but Y1 has a delay of 1 tick. This is because of the propagation delay.
Now, back to your original question. The left gate of your design works exactly as planned because when A0 and B0 are both on, the gate has already changed states. For the right gate, B1 does not always turn on before A1 so there is a propagation delay. I hope this helps! I’ll be here to answer and more questions you might have about khoctykop.
P.S. See the little random spike in the middle of Y1 with your design? That happens because both inputs change at the same time. It’s possible to mitigate that spike by using an additional propagation delay, but the downside to that is the additional delay.