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Thank you for this AMAZING game. I'm having trouble and it's driving me up the wall at times - and I'm getting noise everywhere and I'm not sure It's possible to do without noise ... I'm not stuck, but it's taking a long time to get through level 10. Thanks for the puzzles :D
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Okay, I got the SRAM (I think, test lacks coverage) and the Logical Function Unit... I'm starting to think I'm doing someone's homework for them. Anyone agree?
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Hmm... working on 8 bit SRAM. It looks like the test passes 100% if you implement only 3 storage locations (000, 111, and 010). Also, my circuit had a bug that latched all 3 locations on the first data in strobe and the test still passed because it only looks for a 0 in the location it explicitly clears after all data input strobes are done. Can we get versions of the problem with different tests to more completely validate the circuit?
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I think the difficulty is raising too fast. I could only beat the first 4 levels by my self and I consider myself kinda smart...
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To make it simplier to design on paper with logic circuits, look up "logic circuits lecture" on youtube. Afterward, you must make the circuit that's the hard part grasping when you've completed it. Look back in the Posted comments and load a Design to help understand what you may have missed from an Electrical Engineering Degree.
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yellow silicon is made by pressing the shift key in. Also allows to delete the other. It's complicated for non engineers or noone that has taken any schooling on the subject. I'll try my best to do a short explanation.
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seriously this game is sooo complicated, I watched the tutorial video and sort of understood it but then when I tried to do it I couldn't even draw yellow silicon.
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I'm tied with the level 7 highscore. There's a much nicer 5 gate solution. I'd rather not post the highscore design to just copy-paste, but I'll explain the circuit logic. First just clip the toggle signal to a one-tick pulse. Note this pulse has two logic jobs to do. The pulse needs to turn the toggle on if its off, and needs to turn it off if its on. So the pulse enters along two paths, a turn-on path and a shut-off path. You only want ONE of these paths active at a time. If the toggle is on you need to block the turn-on path. If the toggle is off you need to block the shut-off path. What does the turn-on signal do? It opens a path for VCC+ to come in and power the toggle. That power then needs to hold the toggle in the on state, it loops around to hold open the power. What does the shut-off signal do? It simply cuts the loop where the power is swinging around holding open the power. The power falls closed and stays closed.
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JTZero: What you are proposing would also work, and would in fact be a better solution IMO :)
One could build a period 1 latch (it would not need the delay component), but it would have to be fed with a shortened toggle pulse (otherwise it would toggle 5 times for each pulse!)
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JTZero: Thank you for the kind words :)
A latch in its keep state repeats the latest output signal over and over. The period of repetition (and hence the lenght of the repeated signal) are decided by how many delays you use.
If the repeated signal is not all ones or all zeros, the output will oscillate.
Now, toggling a latch is tricky because you want to toggle the entire signal, but only once. If the toggle pulse is shorter that the latch's period, it will not toggle the entire repeating signal. If the toggle pulse is longer that the latch's period, the signal will start to repeat before the toggle is over, leading parts of it to be toggled twice or more. So the toggle pulse must exactly as long the latch's period to toggle it properly.
I chose a period of 5 ticks for my solution (4 tick delay is caused by the delay gates, and one more tick by the XOR component). This allows me to feed the latch with the unaltered To input (since all the To pulses are exactly 5 ticks long)
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so your inputs would be To and the current from the on state, delayed so it will check only when To is first turned on as to not create oscillation with both inputs on. The dual VCCs works well, never would have thought to switch between the two.
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The big silicone thingy (in the solution below) is a XOR logic gate. As long the toggle input is zero, it outputs the same thing as in its other input (the state of the latch five cycles ago).
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Hey JTZero,
Here is a solution for lvl 7 with only one delay per side:
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nice design. i knew there had to be a delay somewhere in there to prevent oscillation from the toggle. wasn't sure where to go from there. is it possible to use only one delay on each side instead of two?
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Copy this design for the first one.
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See the power coming through the yellow and when the A's turn on they will cut off the power through their red lines.
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the tutorial video isn't too clear. Red on top of a yellow line means power goes through the yellow unless there is power coming through the red in which case it stops. Gate is closed. Yellow on top of a red line means power only goes through the red line when there is also power coming from the yellow. The first is a NOT gate and the second is an AND gate.
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I know the High Score on Level 12 is just because the High Score just started working again, I know the Engineers can do better, don't let me down!
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I bet noone posted the few answers I'm listing, because the Electrical Engineers already have them in their books. Or completed it in class. It is a good educational tool, besides Hex Editor, or parallax Beobot. I think this is top for understanding circuitry. :-)
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Maybe it's 2:30 in the morning, but I can't understand 4-To-1 Multiplyer Z is high when the input pin specified by the S bits (either A, B, C, or D) is high. I think the answer is E. Not enough information.
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Part I of Dual Frequency Oscillator
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Part II of Dual Frequency Ocillator
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TQ==
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Part I Dual Switch Latch Works with Filter, Finally can move on. Any Better Solutions?
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Part II Dual Switch Latch Works with Filter
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Part I Dual Switch Latch This is 96 percent and needs 100 to pass
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This is a flip flop I put two together to make the frequency smaller, in half. Just an ocilator, maybe it is an outdated term?
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This is my XOr Gate, can any one make it smaller?
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